THE LONG RUN: University of Pennsylvania and University of Michigan researchers suggest an approach to power usage where a processor could run at, for example, 16 times its sustainable rate for about half a second and then throttle back so that the processor can cool down, until the next time a surge is needed.
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The demands placed on smart phones by marathon sessions of texting, streaming video and surfing the Web require that they have blazing-fast processors while, at the same time, be able to disburse the heat these processors generate. A team of engineers is proposing something of a counterintuitive model to designing smart phones in the future—one that has processors alternately powering up and then cooling down, more like sprinters than long-distance runners.
Heat dissipation has become a major limitation to the computational power of processors used in smart phones, where there is no room for a fan or other type of cooling system. Only a fraction of the transistors on a smart phone's processor can safely operate at a time. The transistors that are shut down are known as "dark silicon." According to the researchers, more transistors will only lead to more dark silicon because improvements in the processors' ability to dissipate heat are lagging.
University of Pennsylvania and University of Michigan researchers suggest a "computational sprinting" approach to power usage. A processor could run at, for example, 16 times its sustainable rate for about half a second and then throttle back so that the processor can cool down—until the next time a surge is needed. The researchers presented the findings of their computational sprinting feasibility studies (pdf) yesterday at the 18th International Symposium on High Performance Computer Architecture in New Orleans.
Many interactive applications on smart phones depend on short bursts of computational demand punctuated by long idle periods waiting for user input. Computational sprinting would activate otherwise powered-down processor cores (dark silicon) for subsecond bursts of intense parallel computation in response to such sporadic user activity. To handle the heat pulse from sprinting, the researchers propose encasing the processor in a phase-change material—something like candle wax—that would absorb heat by melting during the sprint, then slowly dissipate it by hardening while the device is at rest.
Most of the heat generated by mobile phones comes from the processor, as opposed to the battery, says Thomas Wenisch, a study author and an assistant professor of computer science and engineering at the University of Michigan. "All of the power drawn by the processor turns into heat," he says. "Only a fraction drawn from the battery is lost as heat within the battery due to battery inefficiency (internal resistance in the battery)."
Next up for the researchers is constructing a prototype, focusing on the thermal and material issues, says Milo Martin, another study author and an associate professor in the department of computer and information sciences at the University of Pennsylvania's School of Engineering and Applied Science. "We are also looking at additional applications, mostly in the mobile space but also in other domains, such as servers," he adds.
The researchers also plan to investigate what impact sprinting would have on application design. "This would dictate how programmers should exploit sprints and then deal with the fact that the phone might need to rest, and its impact on end-user satisfaction," Martin says.
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10 Comments
Add CommentHow cute - "dark silicon"!
Reply | Report Abuse | Link to thisHow about "anti-memory"?
As I understand, powering down processors even for very short intervals would require persistent processor memory circuitry to maintain task state information. A small issue for these scientists, I'm sure!
It is possible to save critical cpu state information (program counter, interrupts etc.) in circuitry that is not powered down. Also, powering a core down does not neccessarily mean cutting it's power supply. In CMOS-design, the consumed power is for the biggest part due to loading parasitic capacitances of transistors and vias. Such loading can be cancelled by simply halting the core's clock. In this mode, neither DRAM, nor SRAM is lost. Remaining leakage currents are a minor issue on low voltage cpus in smartphones.
Reply | Report Abuse | Link to thisBtw: very interesting article.
There is no 'non-critical' state information contained in any processor memory - all CPU registers and processor cache memory would have to be sustained by, as I understand, continuously refreshing its data. If this were to be achieved by electrically isolating its circuitry either on or off the processor chip I think their would be enormous performance penalties.
Reply | Report Abuse | Link to thisI don't think that simply halting the processor's clock would sustain volatile memory circuits...
By non-critical state information, i referred to most registers, stack and heap. All of those are saved and restored on function call, return and interrupts thousands of times per second. This information is mapped to general adress-space, which can be transferred between different cache levels, ram and non volatile memory (a feature heavily used under most operating systems).
Reply | Report Abuse | Link to thisThus, a straightforward implementation of a power-down event could either be triggered by the operating system, which has the advantage that it can suspend and withdraw all threads from that particular core as preparation, making any hardware "state saving" unnecessary, or by introducing a dedicated interrupt vector that does the same job. If all cpus are to be halted, the whole system can utilize acpi-conform power management, which already implements this feature (aka standby). by introducing a new power state, the acpi system could perform most the overhead.
cpu registers are in many cases implemeted as SRAM or latches, wich require no refreshing. refreshing is an issue with DRAM, you are right jtdwyer, however it has already been solved for all power states (see "suspend to ram"). Moreover fast caches have to be realized as SRAM, which suffers no loss as long as enaugh voltage is applied. Thus, when the clock is halted, DRAM is not sustained, however SRAM is. that makes this naive technique feasible (in fact, very low clock frequencies are sometimes used in microcontrollers to decrease power consumption and in many systems, there is no lower limit to it).
electrically isolating an area on chip to prevent heat dissipation is not as hard, as it may sound. A single, strong driving transistor in the local power lines can do the job. this is, again, often employed in microcontrollers to cut power consumtion in peripherical systems (SPI/I2C/ADC - modules). This design suffers no performance issues, as it is no real electrical insulation, and has no overhead for signal lines (consider level changes, impedance matching etc).
For a quick reference, please see:
Reply | Report Abuse | Link to thishttp://en.wikipedia.org/wiki/Static_random-access_memory
"Static random-access memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM exhibits data remanence,[1] but is still volatile in the conventional sense that data is eventually lost when the memory is not powered."
You're correct that SRAM does not require continuous refresh, but it is volatile.
The article's statement: "Only a fraction of the transistors on a smart phone's processor can safely operate at a time. The transistors that are shut down are known as "dark silicon."" appears to be premature if not incorrect, as the "dark silicon" link leads to an article that discusses it as yet another proposal to meet foreseen power management requirements in 2020...
You'correct that registers are saved on module entry, but their values and the values of any processor storage is continuously modified as modules execute. What to happens to your applications when you remove the battery on your smart phone?
I'm not knowledgeable of the power management implemented in PDAs and phones, but my impression is that when my laptop 'goes to sleep', it must be copying data in volatile memory to persistent storage (disk) for later restoration.
Finally, scanning through the referenced research report, I see that it's based on a simulation model of the power usage characteristics of a multi-core processor chip in which the number of active cores would be dynamically varied. I'm not prepared to study the paper in detail, I strongly suspect that many "software" issues have not been fully identified, much less resolved.
By the way, from a system software perspective, the dynamic activation & deactivation of multiple 'core' processors within a chip is directly analogous to the process used for years in multi-processor mainframe systems to dynamically deactivate individual processors for service or for error recovery, allowing the system to continue normal, if somewhat degraded, operation.
Reply | Report Abuse | Link to thisIndirectly, this is also analogous to some modern V-8 automobile engines that can be dynamically reconfigured as a 6 or 4 cylinder engine, reducing fuel requirements (albeit also reducing efficiency).
As these examples illustrate, this general concept is not groundbreaking and has been previously used in successful applications.
I think that developing asynchronous microprocessors would be a better way to deal with reducing the power usage while keeping up performance. Asynchronous microprocessors were abandoned a while ago, if I remember correctly, as the circuitry was way too complicated compared to the current clock driven micro's we have today. But if you look at each instruction that the micro is performing and look at the actual circuits that are activated in the uP to perform these functions you will find that the wait states are mostly too long. This is required as the fasted cycle has to be as slow and the slowest function. But with today's technology we could switch over to asynchronous circuits where the function of each logic element includes a 'ready to run' signal and a 'execution complete' signal. The microprocessor then goes as fast as it can and when there is nothing left in the pipeline to execute it just sits and waits for the next operation, in a low powered state. This kind of architecture could consume about 70% less energy than the conventional synchronous circuits used in today's uP core.
Reply | Report Abuse | Link to thisIn my mind, this is the main reason for multicore cpus. Shut the ones off that aren't needed....I'm pretty sure Intels I5 and I7 do this....
Reply | Report Abuse | Link to thisMore simply, I think that multicore chips are a straightforward strategy to add capacity for a given processor architecture. As chip circuit density increased, eventually enough real estate opened up to fit multiple chips, increasing the parallel capacity available to multiprocessor operating systems. Otherwise, the additional circuit capacity could only be used to increase processor cache, extend the architecture with new functions or specialized coprocessors, etc.
Reply | Report Abuse | Link to thisClarification:
Reply | Report Abuse | Link to thisI had intended to say "eventually enough real estate opened up to fit multiple CPUs [on a single chip]..."